A typical MOS dynamic memory cell (DRAM) consists of a single transistor and a capacitor. The state of the memory cell is a function of the charge stored on the capacitor which is shown as element 14 in FIG. 2 below. The single transistor and capacitor in a DRAM have several advantages with respect to static RAMs. Unfortunately the charge on the capacitor in the DRAM leaks and is lost within a short time. To prevent data from being lost, DRAMs are designed to be refreshed periodically. (DRAMs are referred to as volatile RAMs since information stored in the cells is lost when the power supply voltage applied to the memory is lost or turned off.) In instances where stored volatile information must be retained, an alternate power supply, such as a battery system, must be coupled to the memory for use in the event of failure of the main power supply.
By incorporating non-volatile devices with the memory cells, normally operating volatile cells can be made independent of a backup power supply. Non-volatile devices that could be used as backup memory are known in the art.
U.S. Pat. No. 4,990,979 (Otto) discloses an electrically erasable floating-gate memory cell (EEPROM) in which the Fowler-Nordheim tunnel effect is exploited for programming and erasing. The inversion created by a charged floating-gate electrode in the Otto device is horizontal but one edge of the floating gate polysilicon material extends into a trench to accommodate a larger electrode size with a lessened adverse effect on integration density. The control gate, source and drain are located horizontally in the cell.
U.S. Pat. No. 5,049,956 (Yoshida et al.) discloses an EPROM (electrically programmable read only memory) wherein each cell comprises an individual trench containing a control gate and a floating gate separated by a silicon oxide layer. The silicon oxide layer may be replaced with a mixture of silicon oxide and silicon nitride. The cell described is an EPROM and although the application states that the invention is applicable not only to an EPROM but also to an EEPROM (erasable electrically programmable read only memory) the technology to convert the EPROM to an EEPROM is not straightforward. In particular, a gate oxide which is deposited vertically in the trench would have to be properly contoured to create a tunnel oxide in one region. Alternatively, to function as an EEPROM the cell of Yoshida would require a very high voltage to be applied to the drain node of the silicon substrate. This would cause numerous difficulties, particularly if other functions such as the DRAM of the present invention had to be located nearby.
U.S. Pat. No. 5,053,842 (Kojima) discloses a non-volatile memory having a vertically oriented floating gate. The write and erase functions require high voltage and high current.
U.S. Pat. No. 5,017,977 (Richardson) discloses an EPROM array having floating gate field effect transistors formed on the sidewalls of trenches which are cut in a semiconducting substrate. Because the floating gates are charged by injecting hot electrons, high voltages and high currents are required for the write and erase cycles.
U.S. Pat. No. 4,929,988 (Yoshikawa) discloses a non-volatile memory device in which the transistor is formed vertically by forming a floating gate electrode and a control gate electrode on a sidewall of a groove formed in a semiconductor.
The combination of a DRAM and a non-volatile device is called a shadow RAM. Shadow RAMs are known.
U.S. Pat. No. 4,471,471 (DiMaria) discloses an array of field effect transistor memory cells each including a DRAM device comprising a floating gate portion and storage node and each including also a non-volatile unit comprising a double electron injector structure adjacent the floating gate portion but remote from the storage node. The floating gate and the electron injector structure are horizontally oriented and remote from the DRAM. These two features together result in non-volatile RAM devices that provide significantly fewer cells per unit area than those of the invention.
Yamauchi et al. [I.E.D.M. 90. 931-933 (1990)]describe a stacked capacitor DRAM in combination with a flotox EEPROM as a shadow RAM system. The combined cell is more than twice the size of a corresponding simple DRAM array. In addition, the shadow RAM requires an erase cycle before information can be written into the EEPROM. This limits the useful lifetime of the EEPROM because every EEPROM must be cycled for every storage cycle; a direct-write EEPROM need only be cycled when a change is made in the state of the information stored in that EEPROM.
Shadow RAMs that do not require a separate erase cycle are available in the art, but they are incapable of flash storage or recall; i.e. they cannot transfer all data simultaneously; each word line must be correlated through reference to a sense amplifier, slowing the transfer of data.
Several problems associated with providing non- volatile memory remain. Shadow RAMs of the art all have shortcomings: (1) They consume too much space on a chip. All known shadow EEPROM devices are at least twice the size of a DRAM array of the same capacity. (2) They often require a separate erase cycle to accomplish transfer of data between volatile and non- volatile elements. This gives rise to two drawbacks: time is consumed in an extra step and the lifetime of the device is shortened. EEPROMs fatigue from use, a typical flotox EEPROM being good for about 10,000 erase/write operations. If only 10% of the bits of information need to be changed in one cycle, then a device that changes only the bits that are different will last almost ten times as long as a device that erases and writes every cell in every cycle. (3) They are significantly more expensive to fabricate than simple DRAM arrays which makes them uncompetitive in comparison to a standard DRAM with an auxiliary power supply.